The present invention generally relates to methods for locating edge features of a semiconductor wafer relative to the wafer edge, and more specifically relates to a method for locating the edge features using image classification.
Defects that originate from the edge of a semiconductor wafer have a significant impact on device yields and the number of good die that can be obtained from each wafer. Defects from the wafer edge are caused by the way various films are layered on the edge of the wafer. The manner in which various films stack up on the edge of the wafer differ from that of active device areas. Certain combinations of films layered at the edge of a wafer are undesirable because they tend to flake off during subsequent process steps.
To control how the films stack up at the edge of a wafer, a number of wafer edge processing techniques can be used to limit what films are deposited on the edge, selectively expose edge films to normal etch processes, or selectively etch the edge films. Specifically, commonly used techniques include:
1. Wafer edge resist exposure (WEE).
2. Resist and Barc removal using edge solvent dispense.
3. Thin film deposition edge exclusion rings (shadow or gas exclusion).
4. Wafer edge etch to remove unwanted films.
The exact settings used for edge film definition can dramatically affect the yields of a wafer by modulating the number of particle defects coming from the wafer edge. In photo lithography, edge removal process settings are used to control edge film patterning and prevent inappropriate edge film combinations.
In addition to controlling the edge film stacks to reduce defects, it is also important that this be performed in the smallest ring possible around the edge of the wafer. The so-called “edge exclusion ring” is the portion of the wafer edge that is sacrificed for the edge film control. Typically, a 3 or 4 millimeter ring around the edge of the wafer is considered to be unusable. This is a significant area of the wafer that will not produce yielding die.
With very accurate control of the edge settings, it is possible to shrink this edge exclusion zone to 2 millimeters or even smaller while still maintaining film stack combinations that minimize edge defects. Narrower edge settings can achieve an improvement in whole die per wafer. For example, the difference between a 3 millimeter edge setting and a 2 millimeter edge setting can be worth an additional 10 to 30 die per wafer, depending on die size. Even with the lower yields of edge die, the increase in gross die per wafer represents a significant financial value for a typical wafer fabrication laboratory. Presently, at a run rate of 2000 wafers per week, an extra 12 die per wafer would be worth an extra $58,000 per week (or $696,000 per year), with no additional processing cost.
In order to control wafer edge effects, it is critical to precisely control the edge exclusion and edge removal settings. Experience has proven that +/−0.2 millimeter control is needed to achieve consistent results with a 2 millimeter edge setting.
The problem this level of control poses involves how to accurately and inexpensively measure the edge settings of various wafer fabrication processes in order to maintain control of the wafer edge.
A current method for edge setting control is for an operator or technician to view the wafer edge under a microscope. Specifically, the operator estimates the distance from the edge setting to the edge of the wafer based on the magnification used and approximate distance in the field of view. This is repeated at several positions around the edge of the wafer to check for centering of the pattern. The problem with this approach is that the measurement is very subjective and inaccurate (i.e., different people can obtain different measurements of the same thing). The technique can be improved by using an optical vernier or grid on the microscope objectives, but it still cannot provide the accuracy and repeatability needed to meet a +/−0.2 millimeter requirement.
A second approach is to use critical dimension (CD) measurement tools such as a critical dimension (CD) semi-electron microscope (SEM) to measure the distance from the edge of the wafer to an edge feature. The problem with this approach is that these tools can be very expensive (presently about $1,000,000), and are generally designed to measure features that are orders of magnitude smaller. As such, it is very difficult to get the wafer edge and edge feature within the same field of view. Additionally, these tools are usually in great demand to support the critical CD measurement needs for which they were originally purchased.
A third approach is to purchase a dedicated optical measurement tool that is specifically designed for the appropriate scale of measurements. This method can provide adequate resolution, but can be expensive (presently about $500,000). Additionally, generally it is cost prohibitive to buy a tool for this single application. Even with such an instrument, the fact that different people may obtain different sets of measurements while measuring the same thing (i.e., variability from person to person in taking the measurements) remains an issue.